The field of non-volatile memory technology has achieved another major breakthrough! A joint research team from National Yang-Ming Chiao Tung University in Taiwan, TSMC, and the Industrial Technology Research Institute (ITRI) has successfully developed a spin-orbit torque magnetoresistive random access memory (SOT-MRAM) based on β-phase tungsten. This achievement, published in the top international journal Nature Electronics, boasts a data switching speed of just 1 nanosecond, a retention time exceeding 10 years, and a tunneling magnetoresistance ratio of 146%, clearing a key hurdle for the industrialization of next-generation high-speed, low-power memory technology.
According to the research team, the core advantage of SOT-MRAM lies in its triple characteristics of “high speed + non-volatility + low power consumption”, but it has long been limited by the thermal stability bottleneck of spin-orbit coupling materials. The ideal material β-phase tungsten is easily transformed into α-phase tungsten with significantly degraded performance during the 400°C heat treatment in semiconductor manufacturing.
To address this challenge, the team innovatively designed a tungsten-cobalt composite structure: four ultra-thin cobalt layers, each just 0.14 nanometers thick (thicker than a single atomic layer of cobalt), were inserted within a 6.6-nanometer-thick tungsten layer. Experiments showed that this structure could maintain a stable β-phase tungsten at 400°C for 10 hours and even withstand temperatures of 700°C for 30 minutes. Conventional monolayer tungsten undergoes a phase transition after just 10 minutes at 400°C.
The composite structure offers no compromise in performance. Testing has demonstrated a spin Hall conductivity of 4500 Ω⁻¹・cm⁻¹ and a damping-type torque efficiency of 0.61. The fabricated 64-kilobit prototype array not only achieves a 1-nanosecond switching speed (comparable to SRAM), but also exhibits over 99% consistency in flipping behavior across 8,000 devices and data retention exceeding 10 years, fully meeting both industrial and consumer storage requirements.
Current computing systems rely on a three-tier architecture: SRAM cache, DRAM main memory, and flash external storage. However, as process nodes advance beyond 10 nanometers, the drawbacks of this traditional technology have become increasingly apparent: DRAM requires constant refresh, consuming high power; flash memory has read latencies of 50-100 microseconds; and scalability is approaching physical limits. In scenarios such as AI, autonomous driving, and the Internet of Things, the demand for “high-speed response, non-volatile storage, and low power consumption” is becoming increasingly urgent.
“Among emerging non-volatile memory technologies, SOT-MRAM is the only solution that can simultaneously meet these requirements.” TSMC’s R&D director said that compared to other technologies, SOT-MRAM achieves complete separation of read and write paths through a three-terminal structure design, which not only solves the durability problem of STT-MRAM, but also significantly reduces the single-bit energy consumption compared to DRAM, making it particularly suitable for power-sensitive scenarios such as edge computing and mobile terminals.
TSMC has initiated the technology transfer process and plans to embed SOT-MRAM into advanced process nodes. Initially, the focus will be on high-value-added applications such as AI accelerators, autonomous driving domain controllers, and 5G base stations. Subsequently, the technology will gradually penetrate the consumer electronics market, potentially replacing some SRAM cache and DRAM main memory, and reshaping the traditional storage hierarchy.
“This technology was designed with process compatibility in mind from the beginning.” Team member and professor at National Yang-Ming Chiao Tung University in Taiwan pointed out that the 64-kilobit prototype array has now completed comprehensive performance verification. The next step will be to advance to megabit (Mb)-level integration, with the goal of reducing write energy consumption to sub-picojoules per bit.
Experts analyze that this breakthrough not only provides a new direction for the storage industry but also drives the transformation of computing architecture. High-speed, low-power SOT-MRAM can break through the traditional von Neumann architecture “storage wall” bottleneck, offering core support for the implementation of “storage-compute integration” technology—in AI training, it can serve as on-chip cache to reduce high-frequency data access energy consumption; in edge devices, its non-volatile characteristics support rapid start-stop without data loss.
It is worth noting that the team’s proposed “composite layer metastable phase stabilization” strategy can also be reused for research on other functional materials. Currently, the team has initiated exploration of novel oxides and two-dimensional interface materials, which Promising further enhance the performance and reliability of storage devices in the future.
“This is not just a technological breakthrough, but also a turning point for the storage industry moving towards coordinated development of ‘high-speed, low-consumption, non-volatile’.” Industry analysts stated, as companies like TSMC accelerate industrialization, SOT-MRAM Promising become a mainstream storage solution within 3-5 years, reshaping the global semiconductor industry landscape.
